HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy

In this article, we propose a “full-stack” solution to designing high-apacity and low-latency on-chip cache hierarchies by starting at the circuit level of hardware design stack. We novel half V DD precharge 2T Gain Cell (GC) for hierarchy. The GC has several desirable characteristics, including ~50% higher storage density lower dynamic energy as compared traditional 6T SRAM, even after accounting peripheral overheads. also demonstrate data retention time 350 us (~17.5× eDRAM) 28 nm technology with = 0.9V temperature 27°C that, combined optimizations like staggered refresh, makes it an ideal candidate architect all levels caches. show that given area budget, GC-based caches, on average, provide 30% 36% increase in IPC single- multi-programmed workloads, respectively, contemporary SPEC CPU 2017. observe savings 42% 34% respectively. Finally, quest utilize best worlds, combine STT-RAM create hybrid hierarchies. hierarchy caches L1 L2 LLC split between is able 46% benefit energy-delay product (EDP) all-SRAM design, 13% all-GC hierarchy, averaged across workloads.